It is known to use microprocessor based devices to communicate data through a serial data line or through a parallel data bus. In one example in which a serial data signal is transmitted, a microprocessor based controller is provided with the processor and a separate free running counter. The microprocessor determines an on-time for a pulse width modulated signal to be transmitted and loads the on time into the register of the free running counter. The free running counter independently increments the counter output value at regular intervals as controlled by an internal system clock and resets the counter output value when the counter output value overflows. A comparator is coupled to the counter's register and the counter output value. The comparator provides an output signal that has one state, for example, High, when the counter is below the value in the register and a second state, for example, Low, when the counter output is above the value in the register. In this manner, the processor computes the on time, or duty cycle, of a pulse width modulated (PWM) output signal and loads the on time into the register, allowing the free running counter and comparator to continuously generate the PWM output signal independent of the flow of the processor control algorithm except as it controls the value in the counter register.
While the above-described apparatus may be suitable for generating PWM control commands for actuators and for generating PWM serial communications in systems where synchronization between the transmitting and receiving devices is not important, it is not suitable for use where synchronization between the generation of a signal being transmitted and the use of that signal in the receiving controller is required. This is because, with the free running counter and comparator, the above-described apparatus continuously generates the PWM output signal independently of the operation of the control algorithm (except for the contents of the register) and contains no synchronization function allowing the receiving processor to synchronize with the transmitting processor.
For example, the transmitting processor may load a value in the register for its free running counter and then turn to other tasks. It might return to reload the register at irregular intervals while all of the time the free running counter is counting through its cycle and driving the serial output based on the output in the register. The receiving controller has no indication when the transmitting controller has updated the signal in the counter register and, thus, cannot base operation on synchronization with updates to the transmitting controller's free running counter register.